MULTIPLEXER

Program VHDL yang membuat rangkaian sederhana 2 to 1 multiplexer menggunakan pendekatan behavioral level design ;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY multiplexer IS PORT (d0, d1, s: IN STD_LOGIC;y: OUT STD_LOGIC);

END multiplexer;

ARCHITECTURE Behavioral OF multiplexer IS

BEGIN
PROCESS(s, d0, d1)
BEGIN

y <= d0 WHEN s = ’0′ ELSE d1;

END PROCESS;
END Behavioral;

Bisa di ubah memakai IF ELSE ;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY multiplexer is PORT(d0,d1,s : IN STD_LOGIC;y : OUT STD_LOGIC);

END multiplexer;

ARCHITECTURE Behavioral OF multiplexer IS
–blok sekuensial-> ciri dari behavioural level
BEGIN
PROCESS(s, d0, d1)
BEGIN

IF s=’0′ THEN
y <= d0;
ELSE
y <= d1;
END IF;

–y<=d0 WHEN s=’0′ ELSE d1;
END PROCESS;
END Behavioral;